CMOS SOI ICs (complementary metal oxide semiconductor silicon on insulator integrated circuits) have been used in a wide variety of applications. However, attempts to use CMOS SOI ICs in some applications, such as wireless applications, have proven to be unsatisfactory.
For example, GaAs has been used in RF and microwave wireless applications. However, GaAs based devices for these applications are costly and are not easily manufactured. On the other hand, CMOS SO IC processing offers the possibility of easier manufacturing and less cost resulting from integration of a system on a chip. Thus, to effectively compete with GaAs technology, the CMOS SOI manufacturing process must be more cost effective and more highly manufacturable.
Known CMOS SOI manufacturing processes, however, have not offered sufficient advantages over GaAs technology. For example, LOCOS (local oxidation of silicon) isolation and MESA isolation as shown in FIGS. 1 and 2 are processes frequently used in CMOS SOI integration. FIG. 1 shows a CMOS SOI device 10 resulting from conventional LOCOS isolation processing. The CMOS SOI device 10 has an SOI wafer 12 including a bottom silicon layer 14 forming a p-type substrate, a buried oxide insulation layer 16, and a top silicon layer 18. The CMOS SOI device 10 further includes an oxide layer 20 over the top silicon layer 18 and a field oxide 22. As can be seen, conventional LOCOS isolation does not result in global planarity. Also, it is well known that conventional LOCOS isolation results in a long birds beak at the edge of the oxidation.
FIG. 2 shows a CMOS SOI device 30 resulting from conventional MESA isolation processing. The CMOS SOI device 30 has an SOI wafer 32 including a bottom silicon layer 34 forming a p-type substrate, a buried oxide insulation layer 36, and a top silicon layer 38 forming a silicon mesa. The CMOS SOI device 10 further includes a field oxide 40. As can be seen, conventional MESA isolation results in very poor global topography making it effectively impossible to pattern CMOS gates in the sub 0.7 micron regime.
These problems have made it difficult to effectively utilize CMOS SOI ICs in RF and microwave wireless applications.
The present invention solves one or more of these or other problems by utilizing a recessed LOCOS isolation on SOI which facilitates easier and more cost effective CMOS SOI IC manufacturing.
In accordance with one aspect of the present invention, a CMOS SOI process comprises the following: depositing an oxide layer over a silicon layer of an SOI wafer; depositing an isolation layer over the oxide layer; selectively removing the isolation layer, the oxide layer, and a first portion of silicon in the silicon layer so that a recess is formed in the silicon layer and so that the recess is exposed through the isolation layer and the oxide layer; and, growing an isolation oxide over the recess, wherein the silicon in the recess is oxidized.
In accordance with another aspect of the present invention, a method is provided to form a LOCOS isolation in a CMOS SOI device having a top silicon layer, a bottom silicon layer, and an insulation layer between the top and bottom silicon layers. The method comprises the following: forming an oxide layer over the top silicon layer; depositing an LPCVD layer over the oxide layer; providing a photoresist over the LPCVD layer so as to expose a localized area of the LPCVD layer; etching through the localized area of the LPCVD layer to expose the oxide layer; etching through the oxide layer in the localized area to expose the top silicon layer; etching a portion of silicon in the top silicon layer so that a portion of silicon in the top silicon layer remains in localized area and defines a recess;
removing the photoresist; and, growing an isolation oxide over the silicon in the recess, wherein the silicon in the recess is oxidized.
In accordance with still another aspect of the present invention, a method of forming a LOCOS isolation for a CMOS SOI device comprises the following: etching a selected area of a silicon layer of the CMOS SOI device; terminating the etching before an insulation layer of the CMOS SOI device immediately below the silicon layer is exposed through the selected area; and, growing an isolation oxide over the selected area such that the silicon remaining in the selected area is substantially fully oxidized.